This article mainly covers three M.2 interfaces that are very common in embedded systems:

• Socket 1 - Key E
• Socket 2 - Key B
• Socket 3 - Key M

The original document is based on PCI Express M.2 Specification Revision 3.0, Version 1.2.

01 Socket 1 - Key E

Key E is commonly used for connectivity modules such as Wi-Fi / Bluetooth expansion cards. The original text notes that these cards usually connect over PCIe and USB, while support for other buses such as SDIO and I2S depends on whether the COM supports them.

Pinout Description

Notes

• M.2 Socket 1 - Key E is commonly used for connectivity applications such as Wi-Fi / Bluetooth modules.
• The AC coupling capacitors for PCIe_TX+/- are placed on the COM side, while the AC coupling capacitors for PCIe_RX+/- are placed on the M.2 add-in card side, so the carrier board does not need to add those AC coupling capacitors again.
• CLKREQ# is used to enable the PCIe reference clock and should be connected to the output enable pin of the PCIe clock buffer.
• Since CLKREQ# is an active-low open-drain signal driven by the M.2 add-in card, the carrier board side needs a pull-up resistor.

02 Socket 2 - Key B

Key B is common on SATA and PCIe SSDs, as well as some WWAN modules. One key feature of this socket is the set of four configuration pins, CONFIG_0 through CONFIG_3, which let the system identify which host interface the card expects to use.

Pinout Description

Host Interface Configuration

The original text explains that the system should read the four CONFIG_X pins to determine the selected pinout / host interface for the installed card. Even when the M.2 card is not powered yet, the system should still pull these configuration pins up to the appropriate rail so their state can be read.

Note: for the details of each Port Configuration, the original text suggests referring back to the PCI Express M.2 Specification.

Notes

• Socket 2 - Key B is commonly used for PCIe or SATA storage devices.
• CONFIG_1 can be used to switch the host interface:
• CONFIG_1 = Low enables SATA
• CONFIG_1 = High enables PCIe
• The second PCIe lane can support PCIe x2 devices such as Intel Optane. To actually run at x2, the host PCIe lanes must also be configured as a PCIe x2 link.
• When PCIe mode is enabled, the M.2 add-in card does not connect CONFIG_1, so the carrier board side needs a pull-up resistor.
• If this M.2 socket is used with a SATA storage device, Pin 43 should connect to the negative side of the SATA Rx differential pair.
• If this M.2 socket is used with a PCIe storage device, Pin 43 should connect to the positive side of the PCIe Rx differential pair.

03 Socket 3 - Key M

Key M is commonly used for PCIe or SATA storage devices, especially higher-bandwidth SSDs. Similar to Key B, it also has a signal used to select the host interface, but here that signal is PEDET.

Pinout Description

Notes

• Socket 3 - Key M is commonly used for PCIe or SATA storage devices.
• PEDET is used to select the host interface, and the M.2 card indicates the mode by how it is wired:
• PEDET = Low means SATA is enabled, which is done by connecting PEDET to GND on the M.2 card
• PEDET = High means PCIe is enabled, which is done by leaving PEDET unconnected on the M.2 card
• For maximum bandwidth, all four PCIe lanes should be configured as an x4 link.
• When PCIe mode is enabled, the M.2 add-in card does not connect PEDET, so the carrier board side needs a pull-up resistor.
• If this socket is used with a SATA storage device, Pin 43 should connect to the negative side of the SATA Rx differential pair.
• If this socket is used with a PCIe storage device, Pin 43 should connect to the positive side of the PCIe Rx differential pair.

04 Quick Summary

If you only want the quickest takeaways from this article, these are the main points:

• Key E is mainly aimed at connectivity modules such as Wi-Fi / Bluetooth.
• Key B is common on SATA / PCIe SSDs and can also appear on WWAN modules.
• Key M is mainly used for higher-bandwidth storage, especially PCIe SSDs.
• Key B uses CONFIG_0 ~ CONFIG_3 to identify the interface configuration.
• Key M uses PEDET to distinguish between SATA and PCIe.
• Signals such as CLKREQ#, CONFIG_1, and PEDET need pull-ups on the carrier board in some modes.

If you plan to design a carrier board or a socket interface around these definitions, it is still a good idea to compare this summary with the original source and the PCI Express M.2 specification, especially for Port Configuration, PCIe lane mapping, and pins shared between SATA and PCIe.

References

• Source material: https://wiki.congatec.com/wiki/M.2_Pinout_Descriptions_and_Reference_Designs_(AN43)