M.2 Key E, Key B, and Key M Pinout Notes

Wed, 15 Apr 2026 08:00:00 +0800

This article mainly covers three M.2 interfaces that are very common in embedded systems:

Socket 1 - Key E
Socket 2 - Key B
Socket 3 - Key M

The original document is based on PCI Express M.2 Specification Revision 3.0, Version 1.2.

01 Socket 1 - Key E

Key E is commonly used for connectivity modules such as Wi-Fi / Bluetooth expansion cards. The original text notes that these cards usually connect over PCIe and USB, while support for other buses such as SDIO and I2S depends on whether the COM supports them.

Pinout Description

Left Pin	Left Signal	Right Signal	Right Pin
74	3.3V	GND	75
72	3.3V	RESERVED/REFCLKn1	73
70	UIM_POWER_SRC/GPIO_1/PEWAKE1#	RESERVED/REFCLKp1	71
68	UIM_POWER_SNK/CLKREQ1#	GND	69
66	UIM_SWP/PERST1#	RESERVED/PERn1	67
64	RESERVED	RESERVED/PERp1	65
62	ALERT# (I)(0/1.8 V)	GND	63
60	I2C_CLK (O)(0/1.8 V)	RESERVED/PETn1	61
58	I2C_DATA (I/O)(0/1.8 V)	RESERVED/PETp1	59
56	W_DISABLE1# (O)(0/3.3V)	GND	57
54	W_DISABLE2# (O)(0/3.3V)	PEWAKE0# (I/O)(0/3.3V)	55
52	PERST0# (O)(0/3.3V)	CLKREQ0# (I/O)(0/3.3V)	53
50	SUSCLK(32kHz) (O)(0/3.3V)	GND	51
48	COEX_TXD (O)(0/1.8V)	REFCLKn0	49
46	COEX_RXD (I)(0/1.8V)	REFCLKp0	47
44	COEX3 (I/O)(0/1.8V)	GND	45
42	VENDOR DEFINED	PERn0	43
40	VENDOR DEFINED	PERp0	41
38	VENDOR DEFINED	GND	39
36	UART RTS (O)(0/1.8V)	PETn0	37
34	UART CTS (I)(0/1.8V)	PETp0	35
32	UART TXD (O)(0/1.8V)	GND	33
Key E	Key E
Key E	Key E
Key E	Key E
Key E	SDIO RESET#/TX_BLANKING (O)(0/1.8V)	23
22	UART RXD (I)(0/1.8V)	SDIO WAKE# (I)(0/1.8V)	21
20	UART WAKE# (I)(0/3.3V)	SDIO DATA3(I/O)(0/1.8V)	19
18	GND	SDIO DATA2(I/O)(0/1.8V)	17
16	LED_2# (I)(OD)	SDIO DATA1(I/O)(0/1.8V)	15
14	PCM_OUT/I2S SD_OUT (O)(0/1.8V)	SDIO DATA0(I/O)(0/1.8V)	13
12	PCM_IN/I2S SD_IN (I)(0/1.8V)	SDIO CMD(I/O)(0/1.8V)	11
10	PCM_SYNC/I2S WS (I/O)(0/1.8V)	SDIO CLK/SYSCLK (O)(0/1.8V)	9
8	PCM_CLK/I2S SCK (I/O)(0/1.8V)	GND	7
6	LED_1# (I)(OD)	USB_D-	5
4	3.3V	USB_D+	3
2	3.3V	GND	1

Notes

M.2 Socket 1 - Key E is commonly used for connectivity applications such as Wi-Fi / Bluetooth modules.
The AC coupling capacitors for PCIe_TX+/- are placed on the COM side, while the AC coupling capacitors for PCIe_RX+/- are placed on the M.2 add-in card side, so the carrier board does not need to add those AC coupling capacitors again.
CLKREQ# is used to enable the PCIe reference clock and should be connected to the output enable pin of the PCIe clock buffer.
Since CLKREQ# is an active-low open-drain signal driven by the M.2 add-in card, the carrier board side needs a pull-up resistor.

02 Socket 2 - Key B

Key B is common on SATA and PCIe SSDs, as well as some WWAN modules. One key feature of this socket is the set of four configuration pins, CONFIG_0 through CONFIG_3, which let the system identify which host interface the card expects to use.

Pinout Description

Left Pin	Left Signal	Right Signal	Right Pin
74	3.3 V/VBAT	CONFIG_2	75
72	3.3 V/VBAT	GND	73
70	3.3 V/VBAT	GND	71
68	SUSCLK(32kHz) (O)(0/3.3V)	CONFIG_1	69
66	SIM DETECT (O)	RESET# (O)(0/1.8V)	67
64	COEX_RXD (I)(0/1.8V)	ANTCTL3 (I)(0/1.8V)	65
62	COEX_TXD (O)(0/1.8V)	ANTCTL2 (I)(0/1.8V)	63
60	COEX3 (I/O)(0/1.8V)	ANTCTL1 (I)(0/1.8V)	61
58	NC	ANTCTL0 (I)(0/1.8V)	59
56	NC	GND	57
54	PEWAKE# (I/O)(0/3.3V)	REFCLKp	55
52	CLKREQ# (I/O)(0/3.3V)	REFCLKn	53
50	PERST# (O)(0/3.3V)	GND	51
48	GPIO_4 (I/O)(0/1.8V)	PETp0/SATA-A+	49
46	GPIO_3 (I/O)(0/1.8V)	PETn0/SATA-A-	47
44	GPIO_2 (I/O)/ALERT# (I)/(0/1.8V)	GND	45
42	GPIO_1 (I/O)/SMB_DATA (I/O)/(0/1.8V)	PERp0/SATA-B-	43
40	GPIO_0 (I/O)/SMB_CLK (I/O)/(0/1.8V)	PERn0/SATA-B+	41
38	DEVSLP (O)	GND	39
36	UIM-PWR (I)	PETp1/USB3.1-Tx+/SSIC-TxP	37
34	UIM-DATA (I/O)	PETn1/USB3.1-Tx-/SSIC-TxN	35
32	UIM-CLK (I)	GND	33
30	UIM-RESET (I)	PERp1/USB3.1-Rx+/SSIC-RxP	31
28	GPIO_8 (I/O) (0/1.8V)	PERn1/USB3.1-Rx-/SSIC-RxN	29
26	GPIO_10 (I/O) (0/1.8V)	GND	27
24	GPIO_7 (I/O) (0/1.8V)	DPR (O) (0/1.8V)	25
22	GPIO_6 (I/O)(0/1.8V)	GPIO_11 (I/O) (0/1.8V)	23
20	GPIO_5 (I/O)(0/1.8V)	CONFIG_0	21
Key B	Key B
Key B	Key B
Key B	Key B
Key B	GND	11
10	GPIO_9/DAS/DSS (I/O)/LED_1# (I)(0/3.3V)	USB_D-	9
8	W_DISABLE1# (O)(0/3.3V)	USB_D+	7
6	FULL_CARD_POWER_OFF# (O)(0/1.8V or 3.3V)	GND	5
4	3.3 V	GND	3
2	3.3 V	CONFIG_3	1

Host Interface Configuration

The original text explains that the system should read the four CONFIG_X pins to determine the selected pinout / host interface for the installed card. Even when the M.2 card is not powered yet, the system should still pull these configuration pins up to the appropriate rail so their state can be read.

CONFIG_0 (Pin 21)	CONFIG_1 (Pin 69)	CONFIG_2 (Pin 75)	CONFIG_3 (Pin 1)	Host Interface
0	0	0	0	SSD - SATA
0	1	0	0	SSD - PCIe
0	0	1	0	WWAN - PCIe (Port Configuration 0*)
0	1	1	0	WWAN - PCIe (Port Configuration 1*)
0	0	0	1	WWAN - PCIe, USB3.1 Gen1 (Port Configuration 0*)
0	1	0	1	WWAN - PCIe, USB3.1 Gen1 (Port Configuration 1*)
0	0	1	1	WWAN - PCIe, USB3.1 Gen1 (Port Configuration 2*)
0	1	1	1	WWAN - PCIe, USB3.1 Gen1 (Port Configuration 3*)
1	0	0	0	WWAN - SSIC (Port Configuration 0*)
1	1	0	0	WWAN - SSIC (Port Configuration 1*)
1	0	1	0	WWAN - SSIC (Port Configuration 2*)
1	1	1	0	WWAN - SSIC (Port Configuration 3*)
1	0	0	1	WWAN - PCIe (Port Configuration 2*)
1	1	0	1	WWAN - PCIe (Port Configuration 3*)
1	0	1	1	WWAN - PCIe, USB3.1 Gen1 (vendor defined)
1	1	1	1	No Add-in Card Present

Note: for the details of each Port Configuration, the original text suggests referring back to the PCI Express M.2 Specification.

Notes

Socket 2 - Key B is commonly used for PCIe or SATA storage devices.
CONFIG_1 can be used to switch the host interface:
CONFIG_1 = Low enables SATA
CONFIG_1 = High enables PCIe
The second PCIe lane can support PCIe x2 devices such as Intel Optane. To actually run at x2, the host PCIe lanes must also be configured as a PCIe x2 link.
When PCIe mode is enabled, the M.2 add-in card does not connect CONFIG_1, so the carrier board side needs a pull-up resistor.
If this M.2 socket is used with a SATA storage device, Pin 43 should connect to the negative side of the SATA Rx differential pair.
If this M.2 socket is used with a PCIe storage device, Pin 43 should connect to the positive side of the PCIe Rx differential pair.

03 Socket 3 - Key M

Key M is commonly used for PCIe or SATA storage devices, especially higher-bandwidth SSDs. Similar to Key B, it also has a signal used to select the host interface, but here that signal is PEDET.

Pinout Description

Left Pin	Left Signal	Right Signal	Right Pin
74	3.3 V	GND	75
72	3.3 V	GND	73
70	3.3 V	GND	71
68	SUSCLK (O)(0/3.3V)	PEDET	69
Key M	NC	67
Key M	Key M
Key M	Key M
Key M	Key M
Key M	Key M
58	NC	GND	57
56	NC	REFCLKp	55
54	PEWAKE# (I/O)(0/3.3V) or NC	REFCLKn	53
52	CLKREQ# (I/O)(0/3.3V) or NC	GND	51
50	PERST# (O)(0/3.3V) or NC	PETp0/SATA-A+	49
48	NC	PETn0/SATA-A-	47
46	NC	GND	45
44	ALERT# (I) (0/1.8V)	PERp0/SATA-B-	43
42	SMB_DATA (I/O) (0/1.8V)	PERn0/SATA-B+	41
40	SMB_CLK (I/O)(0/1.8V)	GND	39
38	DEVSLP (O)	PETp1	37
36	NC	PETn1	35
34	NC	GND	33
32	NC	PERp1	31
30	NC	PERn1	29
28	NC	GND	27
26	NC	PETp2	25
24	NC	PETn2	23
22	NC	GND	21
20	NC	PERp2	19
18	3.3 V	PERn2	17
16	3.3 V	GND	15
14	3.3 V	PETp3	13
12	3.3 V	PETn3	11
10	DAS/DSS (I/O)/LED_1# (I)(0/3.3V)	GND	9
8	NC	PERp3	7
6	NC	PERn3	5
4	3.3 V	GND	3
2	3.3 V	GND	1

Notes

Socket 3 - Key M is commonly used for PCIe or SATA storage devices.
PEDET is used to select the host interface, and the M.2 card indicates the mode by how it is wired:
PEDET = Low means SATA is enabled, which is done by connecting PEDET to GND on the M.2 card
PEDET = High means PCIe is enabled, which is done by leaving PEDET unconnected on the M.2 card
For maximum bandwidth, all four PCIe lanes should be configured as an x4 link.
When PCIe mode is enabled, the M.2 add-in card does not connect PEDET, so the carrier board side needs a pull-up resistor.
If this socket is used with a SATA storage device, Pin 43 should connect to the negative side of the SATA Rx differential pair.
If this socket is used with a PCIe storage device, Pin 43 should connect to the positive side of the PCIe Rx differential pair.

04 Quick Summary

If you only want the quickest takeaways from this article, these are the main points:

Key E is mainly aimed at connectivity modules such as Wi-Fi / Bluetooth.
Key B is common on SATA / PCIe SSDs and can also appear on WWAN modules.
Key M is mainly used for higher-bandwidth storage, especially PCIe SSDs.
Key B uses CONFIG_0 ~ CONFIG_3 to identify the interface configuration.
Key M uses PEDET to distinguish between SATA and PCIe.
Signals such as CLKREQ#, CONFIG_1, and PEDET need pull-ups on the carrier board in some modes.

If you plan to design a carrier board or a socket interface around these definitions, it is still a good idea to compare this summary with the original source and the PCI Express M.2 specification, especially for Port Configuration, PCIe lane mapping, and pins shared between SATA and PCIe.

References

Source material: https://wiki.congatec.com/wiki/M.2_Pinout_Descriptions_and_Reference_Designs_(AN43)

M.2 on KnightLi Blog

M.2 Key E, Key B, and Key M Pinout Notes

01 Socket 1 - Key E

Pinout Description

Notes

02 Socket 2 - Key B

Pinout Description

Host Interface Configuration

Notes

03 Socket 3 - Key M

Pinout Description

Notes

04 Quick Summary

References